ds065 (v5.0) may 17, 2013 www.xilinx.com 1 product specification ? 1998, 2003?2006, 2013 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimer s are as listed at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ? product obsolete / under obsolescence ? features ? 7.5 ns pin-to-pin logic delays on all pins ?f cnt to 125 mhz ? 72 macrocells with 1,600 usable gates ? up to 72 user i/o pins ? 5v in-system programmable - endurance of 10,000 program/erase cycles - program/erase over full commercial voltage and temperature range ? enhanced pin-locking architecture ? flexible 36v18 function block - 90 product terms drive any or all of 18 macrocells within function block - global and product term clocks, output enables, set and reset signals ? extensive ieee std 1149.1 boundary-scan (jtag) support ? programmable power reduction mode in each macrocell ? slew rate control on individual outputs ? user programmable ground pin capability ? extended pattern security features for design protection ? high-drive 24 ma outputs ? 3.3v or 5v i/o capability ? advanced cmos 5v fastflash? technology ? supports parallel programming of more than one xc9500 concurrently ? available in 44-pin plcc, 84-pin plcc, 100-pin pqfp, and 100-pin tqfp packages description the xc9572 is a high-performance cpld providing advanced in-system programmin g and test capabilities for general purpose logic integration. it is comprised of eight 36v18 function blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. see figure 2 for the architec- ture overview. power management power dissipation can be reduced in the xc9572 by config- uring macrocells to standard or low-power modes of opera- tion. unused macrocells are turned off to minimize power dissipation. operating current for each design can be approximated for specific operating conditions using the following equation: i cc (ma) = mc hp (1.7) + mc lp (0.9) + mc (0.006 ma/mhz) f where: mc hp = macrocells in high-performance mode mc lp = macrocells in low-power mode mc = total number of macrocells used f = clock frequency (mhz) figure 1 shows a typical calculation for the xc9572 device. 0 xc9572 in-system programmable cpld ds065 (v5.0) may 17, 2013 05 product specification r figure 1: typical i cc vs. frequency for xc9572 clock frequency (mhz) typical i cc (ma) 050 100 (65) (125) (160) (100) 200 100 high performance low power ds065_01_110501
xc9572 in-system programmable cpld 2 www.xilinx.com ds065 (v5.0) may 17, 2013 product specification r ? product obsolete / under obsolescence ? figure 2: xc9572 architecture function block outputs (indicated by the bold line) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 36 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 2 1 i/o i/o i/o i/o 3 ds065_02_110101 1 function block 2 36 18 18 function block 3 macrocells 1 to 18 36 18 function block 4 macrocells 1 to 18 36 18 fast connect ii switch matrix
xc9572 in-system programmable cpld ds065 (v5.0) may 17, 2013 www.xilinx.com 3 product specification r ? product obsolete / under obsolescence ? absolute maximum ratings recommended operation conditions quality and reliability characteristics dc characteristic over reco mmended operating conditions symbol description value units v cc supply voltage relative to gnd ?0.5 to 7.0 v v in input voltage relative to gnd ?0.5 to v cc + 0.5 v v ts voltage applied to 3-state output ?0.5 to v cc + 0.5 v t stg storage temperature (ambient) ?65 to +150 o c t j junction temperature +150 o c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol parameter min max units v ccint supply voltage fo r internal logic and input buffers commercial t a = 0 o c to 70 o c 4.75 5.25 v industrial t a = ?40 o c to +85 o c4.5 5.5 v ccio supply voltage for output drivers for 5v operation commercial t a = 0 o c to 70 o c 4.75 5.25 v industrial t a = ?40 o c to +85 o c4.5 5.5 supply voltage for output drivers for 3.3v operation 3.0 3.6 v il low-level input voltage 0 0.80 v v ih high-level input voltage 2.0 v ccint + 0.5 v v o output voltage 0 v ccio v symbol parameter min max units t dr data retention 20 - years n pe program/erase cycles (endurance) 10,000 - cycles symbol parameter test conditions min max units v oh output high voltage for 5v outputs i oh = ?4.0 ma, v cc = min 2.4 - v output high voltage for 3.3v outputs i oh = ?3.2 ma, v cc = min 2.4 - v v ol output low voltage for 5v outputs i ol = 24 ma, v cc = min - 0.5 v output low voltage for 3.3v outputs i ol = 10 ma, v cc = min - 0.4 v i il input leakage current v cc = max v in = gnd or v cc -10 a i ih i/o high-z leakage current v cc = max v in = gnd or v cc -10 a c in i/o capacitance v in = gnd f = 1.0 mhz -10pf i cc operating supply current (low power mode, active) v i = gnd, no load f = 1.0 mhz 65 (typical) ma
xc9572 in-system programmable cpld 4 www.xilinx.com ds065 (v5.0) may 17, 2013 product specification r ? product obsolete / under obsolescence ? ac characteristics symbol parameter xc9572-7 xc9572-10 xc9572-15 units min max min max min max t pd i/o to output valid - 7.5 - 10.0 - 15.0 ns t su i/o setup time before gck 4.5 - 6.0 - 8.0 - ns t h i/o hold time after gck 0 - 0 - 0 - ns t co gck to output valid - 4.5 - 6.0 - 8.0 ns f cnt (1) 16-bit counter frequency 125.0 - 111.1 - 95.2 - mhz f system (2) multiple fb internal operating frequency 83.3 - 66.7 - 55.6 - mhz t psu i/o setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns t ph i/o hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns t pco p-term clock output valid - 8.5 - 10.0 - 12.0 ns t oe gts to output valid - 5.5 - 6.0 - 11.0 ns t od gts to output disable - 5.5 - 6.0 - 11.0 ns t poe product term oe to output enabled - 9.5 - 10.0 - 14.0 ns t pod product term oe to output disabled - 9.5 - 10.0 - 14.0 ns t wlh gck pulse width (high or low) 4.0 - 4.5 - 5.5 - ns t aprpw asynchronous preset/reset pulse width (high or low) 7.0 - 7.5 - 8.0 - ns notes: 1. f cnt is the fastest 16-bit counter frequency availa ble, using the local feedback when applicable. f cnt is also the export control maximum flip-flop toggle rate, f tog . 2. f system is the internal operating frequency for general purpose system designs spanning multiple fbs. figure 3: ac load circuit device output output type v test 5.0v 3.3v v test r 1 160 260 r 1 r 2 c l r 2 120 360 c l 35 pf 35 pf ds067_03_110101 v ccio 5.0v 3.3v
xc9572 in-system programmable cpld ds065 (v5.0) may 17, 2013 www.xilinx.com 5 product specification r ? product obsolete / under obsolescence ? internal timing parameters symbol parameter xc9572-7 xc9572-10 xc9572-15 units min max min max min max buffer delays t in input buffer delay - 2.5 - 3.5 - 4.5 ns t gck gck buffer delay - 1.5 - 2.5 - 3.0 ns t gsr gsr buffer delay - 4.5 - 6.0 - 7.5 ns t gts gts buffer delay - 5.5 - 6.0 - 11.0 ns t out output buffer delay - 2.5 - 3.0 - 4.5 ns t en output buffer enable/disable delay - 0 - 0 - 0 ns product term control delays t ptck product term clock delay - 3.0 - 3.0 - 2.5 ns t ptsr product term set/reset delay - 2.0 - 2.5 - 3.0 ns t ptts product term 3-state delay - 4.5 - 3.5 - 5.0 ns internal register and combinatorial delays t pdi combinatorial logic propagation delay - 0.5 - 1.0 - 3.0 ns t sui register setup time 1.5 - 2.5 - 3.5 - ns t hi register hold time 3.0 - 3.5 - 4.5 - ns t coi register clock to output valid time - 0.5 - 0.5 - 0.5 ns t aoi register async. s/r to output delay - 6.5 - 7.0 - 8.0 ns t rai register async. s/r recover before clock 7.5 - 10.0 - 10.0 - ns t logi internal logic delay - 2.0 - 2.5 - 3.0 ns t logilp internal low power logic delay - 10.0 - 11.0 - 11.5 ns feedback delays t f fastconnect feedback delay - 8.0 - 9.5 - 11.0 ns t lf function block local feedback delay - 4.0 - 3.5 - 3.5 ns time adders t pta (1) incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns t slew slew-rate limited delay - 4.0 - 4.5 - 5.0 ns notes: 1. t pta is multiplied by the span of the function as defined in the xc9500 family data sheet.
xc9572 in-system programmable cpld 6 www.xilinx.com ds065 (v5.0) may 17, 2013 product specification r ? product obsolete / under obsolescence ? xc9572 i/o pins function block macro- cell pc44 pc84 pq100 tq100 bscan order function block macro- cell pc44 pc84 pq100 tq100 bscan order 1 1 ? 4 18 16 213 3 1 ? 25 43 41 105 1 2 1 1 15 13 210 3 2 11 17 34 32 102 1 3 ? 6 20 18 207 3 3 ? 31 51 49 99 1 4 ? 7 22 20 204 3 4 ? 32 52 50 96 1 5 2 2 16 14 201 3 5 12 19 37 35 93 1 6 3 3 17 15 198 3 6 ? 34 55 53 90 1 7 ? 11 27 25 195 3 7 ? 35 56 54 87 1 8 4 5 19 17 192 3 8 13 21 39 37 84 1 9 5 [1] 9 [1] 24 [1] 22 [1] 189 3 9 14 26 44 42 81 1 10 ? 13 30 28 186 3 10 ? 40 62 60 78 1 11 6 [1] 10 [1] 25 [1] 23 [1] 183 3 11 18 33 54 52 75 1 12 ? 18 35 33 180 3 12 ? 41 63 61 72 1 13 ? 20 38 36 177 3 13 ? 43 65 63 69 1 14 7 [1] 12 [1] 29 [1] 27 [1] 174 3 14 19 36 57 55 66 1 15 8 14 31 29 171 3 15 20 37 58 56 63 1 16 ? 23 41 39 168 3 16 ? 45 67 65 60 1 17 9 15 32 30 165 3 17 22 39 60 58 57 1 18 ? 24 42 40 162 318??615954 2 1 ? 63 89 87 159 4 1 ? 46 68 66 51 2 2 35 69 96 94 156 4 2 24 44 66 64 48 2 3 ? 67 93 91 153 4 3 ? 51 73 71 45 2 4 ? 68 95 93 150 4 4 ? 52 74 72 42 2 5 36 70 97 95 147 4 5 25 47 69 67 39 2 6 37 71 98 96 144 4 6 ? 54 78 76 36 2 7 ? 76 [2] 5 [2] 3 [2] 141 4 7 ? 55 79 77 33 2 8 38 72 99 97 138 4 8 26 48 70 68 30 2 9 39 [1] 74 [1] 1 [1] 99 [1] 135 4 9 27 50 72 70 27 2 10 ? 75 3 1132 4 10 ? 57 83 81 24 2 11 40 [1] 77 [1] 6 [1] 4 [1] 129 4 11 28 53 76 74 21 2 12 ? 79 8 6126 4 12 ? 58 84 82 18 2 13 ? 80 10 8123 4 13 ? 61 87 85 15 2 14 42 [3] 81 [3] 11 [3] 9 [3] 120 4 14 29 56 80 78 12 2 15 43 83 13 11 117 4 15 33 65 91 89 9 2 16 ? 82 12 10 114 4 16 ? 62 88 86 6 2 17 44 84 14 12 111 4 17 34 66 92 90 3 218??9492108 418??81790 notes: 1. global control pin. 2. global control pin gts1 for pc84, pq100, and tq100. 3. global control pin gts1 for pc44.
xc9572 in-system programmable cpld ds065 (v5.0) may 17, 2013 www.xilinx.com 7 product specification r ? product obsolete / under obsolescence ? xc9572 global, jtag and power pins pin type pc44 pc84 pq100 tq100 i/o/gck1 5 9 24 22 i/o/gck2 6 10 25 23 i/o/gck3 7 12 29 27 i/o/gts1 42 76 5 3 i/o/gts2 40 77 6 4 i/o/gsr 39 74 1 99 tck 17 30 50 48 tdi 15 28 47 45 tdo 30 59 85 83 tms 16 29 49 47 v ccint 5v 21,41 38,73,78 7,59,100 5,57,98 v ccio 3.3v/5v 32 22,64 28,40,53,90 26,38,51,88 gnd 10,23,31 8,16,27,42, 49,60 2,23,33,46,64,71, 77,86 100,21,31,44,62,69, 75, 84 no connects - - 4,9,21,26,36,45,48, 75, 82 2,7,19,24,34,43,46, 73, 80
xc9572 in-system programmable cpld 8 www.xilinx.com ds065 (v5.0) may 17, 2013 product specification r ? product obsolete / under obsolescence ? device part marking and ordering combination information device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1) xc9572-7pc44c 7.5 ns pc44 44-pin plastic lead chip carrier (plcc) c xc9572-7pcg44c 7.5 ns pcg44 44-pin plastic lead chip carrier (plcc); pb-free c xc9572-7pc84c 7.5 ns pc84 84-pin plastic lead chip carrier (plcc) c xc9572-7pcg84c 7.5 ns pcg84 84-pin plastic lead chip carrier (plcc); pb-free c xc9572-7pq100c 7.5 ns pq100 100-pin plastic quad flat pack (pqfp) c xc9572-7pqg100c 7.5 ns pqg100 100-pin plastic quad flat pack (pqfp); pb-free c xc9572-7tq100c 7.5 ns tq100 100-pin thin quad flat pack (tqfp) c xc9572-7tqg100c 7.5 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc9572-10pc44c 10 ns pc44 44-pin plastic lead chip carrier (plcc) c xc9572-10pcg44c 10 ns pcg44 44-pin plastic lead chip carrier (plcc); pb-free c xc9572-10pc84c 10 ns pc84 84-pin plastic lead chip carrier (plcc) c xc9572-10pcg84c 10 ns pcg84 84-pin plastic lead chip carrier (plcc); pb-free c xc9572-10pq100c 10 ns pq100 100-pin plastic quad flat pack (pqfp) c xc9572-10pqg100c 10 ns pqg100 100-pin plastic quad flat pack (pqfp); pb-free c xc9572-10tq100c 10 ns tq100 100-pin thin quad flat pack (tqfp) c xc9572-10tqg100c 10 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc9572-10pc44i 10 ns pc44 44-pin plastic lead chip carrier (plcc) i xc9572-10pcg44i 10 ns pcg44 44-pin plastic lead chip carrier (plcc); pb-free i xc9572-10pc84i 10 ns pc84 84-pin plastic lead chip carrier (plcc) i xc9572-10pcg84i 10 ns pcg84 84-pin plastic lead chip carrier (plcc); pb-free i xc9572-10pq100i 10 ns pq100 100-pin plastic quad flat pack (pqfp) i xc9572-10pqg100i 10 ns pqg100 100-pin plastic quad flat pack (pqfp); pb-free i xc9572-10tq100i 10 ns tq100 100-pin thin quad flat pack (tqfp) i xc9572-10tqg100i 10 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free i XC9572-15PC44C 15 ns pc44 44-pin plastic lead chip carrier (plcc) c xc9572-15pcg44c 15 ns pcg44 44-pin plastic lead chip carrier (plcc); pb-free c xc9572-15pc84c 15 ns pc84 84-pin plastic lead chip carrier (plcc) c xc9572-15pcg84c 15 ns pcg84 84-pin plastic lead chip carrier (plcc); pb-free c xc9572-15pq100c 15 ns pq100 100-pin plastic quad flat pack (pqfp) c xc9572-15pqg100c 15 ns pqg100 100-pin plastic quad flat pack (pqfp); pb-free c xc9572-15tq100c 15 ns tq100 100-pin thin quad flat pack (tqfp) c xc9572-15tqg100c 15 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free c xc95xxx tq144 7c device type package speed operating range this line not related to device part number sample package with part marking. r 1
xc9572 in-system programmable cpld ds065 (v5.0) may 17, 2013 www.xilinx.com 9 product specification r ? product obsolete / under obsolescence ? warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the products. products are not designed to be fail-safe and are not warranted for use in applications that pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. revision history the following table shows the revision history for this document. xc9572-15pc44i 15 ns pc44 44-pin plastic lead chip carrier (plcc) i xc9572-15pcg44i 15 ns pcg44 44-pin plastic lead chip carrier (plcc); pb-free i xc9572-15pc84i 15 ns pc84 84-pin plastic lead chip carrier (plcc) i xc9572-15pcg84i 15 ns pcg84 84-pin plastic lead chip carrier (plcc); pb-free i xc9572-15pq100i 15 ns pq100 100-pin plastic quad flat pack (pqfp) i xc9572-15pqg100i 15 ns pqg100 100-pin plastic quad flat pack (pqfp); pb-free i xc9572-15tq100i 15 ns tq100 100-pin thin quad flat pack (tqfp) i xc9572-15tqg100i 15 ns tqg100 100-pin thin quad flat pack (tqfp); pb-free i notes: 1. c = commercial: t a = 0 to +70c; i = industrial: t a = ?40 to +85c date version revision 12/04/1998 3.0 update ac characteristics and internal parameters. 06/18/2003 4.0 updated format. 08/21/2003 4.1 updated package device marking pin 1 orientation. 04/15/2005 4.2 added asynchronous preset/reset pulse width specification (t aprpw ) 04/03/2006 4.3 added warranty disclaimer. added pb-free package information. 05/17/2013 5.0 the products listed in this data sheet are obsolete. see xcn11010 for further information. device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1)
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